Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 
 
Software Version and Target Device
Product Version: ISE:12.1 (WebPack) - M.53d Target Family: Spartan3A and Spartan3AN
OS Platform: NT Target Device: xc3s400an
Project ID (random number) 684acf2150724198a130877b888bb684.a627f39c7799472ea1879383773986f6.2 Target Package: fgg400
Registration ID 176036481_0_0_631 Target Speed: -4
Date Generated 2015-07-11T19:38:31 Tool Flow CommandLine
 
User Environment
OS Name Microsoft Windows XP Professional OS Release Service Pack 3 (build 2600)
CPU Name Intel(R) Xeon(R) CPU W3520 @ 2.67GHz CPU Speed 2666 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
  MiscellaneousStatistics
  • AGG_BONDED_IO=55
  • AGG_IO=55
  • AGG_SLICE=3268
  • NUM_4_INPUT_LUT=5661
  • NUM_BONDED_IBUF=5
  • NUM_BONDED_IOB=50
  • NUM_BUFGMUX=2
  • NUM_CYMUX=794
  • NUM_DCM=1
  • NUM_DP_RAM=272
  • NUM_IOB_FF=22
  • NUM_LUT_RT=269
  • NUM_MULT18X18SIO=2
  • NUM_MULTAND=43
  • NUM_RAMB16BWE=16
  • NUM_SLICEL=3132
  • NUM_SLICEM=136
  • NUM_SLICE_FF=2418
  • NUM_XOR=724
 		NetStatistics
  • NumNets_Active=6671
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BRAMADDR=416
  • NumNodesOfType_Active_BRAMDUMMY=280
  • NumNodesOfType_Active_CLKPIN=1714
  • NumNodesOfType_Active_CNTRLPIN=2581
  • NumNodesOfType_Active_DOUBLE=18569
  • NumNodesOfType_Active_DUMMY=18226
  • NumNodesOfType_Active_DUMMYBANK=283
  • NumNodesOfType_Active_DUMMYESC=27
  • NumNodesOfType_Active_GLOBAL=209
  • NumNodesOfType_Active_HFULLHEX=310
  • NumNodesOfType_Active_HLONG=66
  • NumNodesOfType_Active_HUNIHEX=1828
  • NumNodesOfType_Active_INPUT=20333
  • NumNodesOfType_Active_IOBOUTPUT=42
  • NumNodesOfType_Active_OMUX=6218
  • NumNodesOfType_Active_OUTPUT=6533
  • NumNodesOfType_Active_PREBXBY=4884
  • NumNodesOfType_Active_VFULLHEX=1395
  • NumNodesOfType_Active_VLONG=309
  • NumNodesOfType_Active_VUNIHEX=1957
  • NumNodesOfType_Gnd_BRAMDUMMY=130
  • NumNodesOfType_Gnd_CLKPIN=1
  • NumNodesOfType_Gnd_CNTRLPIN=2
  • NumNodesOfType_Gnd_DOUBLE=69
  • NumNodesOfType_Gnd_DUMMY=2
  • NumNodesOfType_Gnd_DUMMYBANK=7
  • NumNodesOfType_Gnd_INPUT=149
  • NumNodesOfType_Gnd_OMUX=45
  • NumNodesOfType_Gnd_OUTPUT=33
  • NumNodesOfType_Gnd_PREBXBY=19
  • NumNodesOfType_Gnd_VFULLHEX=11
  • NumNodesOfType_Gnd_VLONG=2
  • NumNodesOfType_Gnd_VUNIHEX=1
  • NumNodesOfType_Vcc_BRAMDUMMY=2
  • NumNodesOfType_Vcc_CNTRLPIN=2
  • NumNodesOfType_Vcc_INPUT=13
  • NumNodesOfType_Vcc_PREBXBY=8
  • NumNodesOfType_Vcc_VCCOUT=14
 SiteStatistics
  • IBUF-DIFFMI_NDT=1
  • IBUF-DIFFMTB=2
  • IBUF-DIFFSTB=2
  • IOB-DIFFMLR=19
  • IOB-DIFFMTB=7
  • IOB-DIFFSLR=17
  • IOB-DIFFSTB=7
  • SLICEL-SLICEM=1474
 		SiteSummary
  • BUFGMUX=2
  • BUFGMUX_GCLKMUX=2
  • BUFGMUX_GCLK_BUFFER=2
  • DCM=1
  • DCM_DCM=1
  • IBUF=5
  • IBUF_DELAY_ADJ_BBOX=5
  • IBUF_INBUF=5
  • IBUF_PAD=5
  • IOB=50
  • IOB_DELAY_ADJ_BBOX=21
  • IOB_IFF1=16
  • IOB_INBUF=21
  • IOB_OFF1=5
  • IOB_OUTBUF=50
  • IOB_PAD=50
  • IOB_TFF1=1
  • MULT18X18SIO=2
  • MULT18X18SIO_MULT18X18SIO=2
  • RAMB16BWE=16
  • RAMB16BWE_RAMB16BWE=16
  • SLICEL=3132
  • SLICEL_C1VDD=37
  • SLICEL_C2VDD=36
  • SLICEL_CYMUXF=406
  • SLICEL_CYMUXG=388
  • SLICEL_F=2731
  • SLICEL_F5MUX=265
  • SLICEL_F6MUX=6
  • SLICEL_FAND=22
  • SLICEL_FFX=1366
  • SLICEL_FFY=1052
  • SLICEL_G=2658
  • SLICEL_GAND=21
  • SLICEL_GNDF=258
  • SLICEL_GNDG=245
  • SLICEL_XORF=363
  • SLICEL_XORG=361
  • SLICEM=136
  • SLICEM_F=136
  • SLICEM_G=136
  • SLICEM_WSGEN=136
 
Configuration Data
BUFGMUX
  • S=[S_INV:2] [S:0]
 BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:2]
  • S=[S_INV:2] [S:0]
 DCM
  • PSCLK=[PSCLK_INV:0] [PSCLK:1]
  • PSEN=[PSEN_INV:0] [PSEN:1]
  • PSINCDEC=[PSINCDEC_INV:0] [PSINCDEC:1]
  • RST=[RST:1] [RST_INV:0]
 DCM_DCM
  • CLKDV_DIVIDE=[16:1]
  • CLKOUT_PHASE_SHIFT=[NONE:1]
  • CLK_FEEDBACK=[1X:1]
  • DESKEW_ADJUST=[9:1]
  • DFS_FREQUENCY_MODE=[LOW:1]
  • DLL_FREQUENCY_MODE=[LOW:1]
  • DUTY_CYCLE_CORRECTION=[TRUE:1]
  • FACTORY_JF1=[0XC0:1]
  • FACTORY_JF2=[0X80:1]
  • PSCLK=[PSCLK_INV:0] [PSCLK:1]
  • PSEN=[PSEN_INV:0] [PSEN:1]
  • PSINCDEC=[PSINCDEC_INV:0] [PSINCDEC:1]
  • RST=[RST:1] [RST_INV:0]
 IBUF_DELAY_ADJ_BBOX
  • DELAY_ADJ_ATTRBOX=[FIXED:5]
  • IBUF_DELAY_VALUE=[DLY0:5]
  • IFD_DELAY_VALUE=[DLY0:5]
  • SEL_IN=[SEL_IN:5] [SEL_IN_INV:0]
 IBUF_PAD
  • IOATTRBOX=[LVCMOS25:5]
  • PULL=[PULLUP:1]
 IOB
  • ICE=[ICE:16] [ICE_INV:0]
  • ICLK1=[ICLK1_INV:0] [ICLK1:16]
  • O1=[O1_INV:1] [O1:49]
  • OCE=[OCE:4] [OCE_INV:0]
  • OTCLK1=[OTCLK1_INV:0] [OTCLK1:6]
  • SR=[SR:1] [SR_INV:0]
  • T1=[T1_INV:16] [T1:5]
  • TCE=[TCE_INV:0] [TCE:1]
 IOB_DELAY_ADJ_BBOX
  • DELAY_ADJ_ATTRBOX=[FIXED:21]
  • IBUF_DELAY_VALUE=[DLY0:21]
  • IFD_DELAY_VALUE=[DLY0:5] [DLY5:16]
  • SEL_IN=[SEL_IN:21] [SEL_IN_INV:0]
 IOB_IFF1
  • CE=[CE:16] [CE_INV:0]
  • CK=[CK:16] [CK_INV:0]
  • IFF1_INIT_ATTR=[INIT0:16]
  • LATCH_OR_FF=[FF:16]
 IOB_OFF1
  • CE=[CE:4] [CE_INV:0]
  • CK=[CK:5] [CK_INV:0]
  • D=[D:5] [D_INV:0]
  • LATCH_OR_FF=[FF:5]
  • OFF1_INIT_ATTR=[INIT0:5]
 IOB_OUTBUF
  • IN=[IN_INV:1] [IN:49]
  • SUSPEND=[3STATE:50]
  • TRI=[TRI_INV:16] [TRI:5]
 IOB_PAD
  • DRIVEATTRBOX=[12:50]
  • IOATTRBOX=[LVCMOS25:50]
  • PULL=[PULLUP:5]
  • SLEW=[SLOW:50]
 IOB_TFF1
  • CE=[CE:1] [CE_INV:0]
  • CK=[CK:1] [CK_INV:0]
  • D=[D:1] [D_INV:0]
  • LATCH_OR_FF=[FF:1]
  • SR=[SR:1] [SR_INV:0]
  • TFF1_INIT_ATTR=[INIT1:1]
  • TFF1_SR_ATTR=[SRHIGH:1]
  • TFFATTRBOX=[SYNC:1]
 MULT18X18SIO
  • CEA=[CEA_INV:0] [CEA:2]
  • CEB=[CEB_INV:0] [CEB:2]
  • CEP=[CEP:2] [CEP_INV:0]
  • CLK=[CLK:2] [CLK_INV:0]
  • RSTA=[RSTA:2] [RSTA_INV:0]
  • RSTB=[RSTB:2] [RSTB_INV:0]
  • RSTP=[RSTP_INV:0] [RSTP:2]
 MULT18X18SIO_MULT18X18SIO
  • AREG=[1:2]
  • BREG=[1:2]
  • B_INPUT=[DIRECT:2]
  • CEA=[CEA_INV:0] [CEA:2]
  • CEB=[CEB_INV:0] [CEB:2]
  • CEP=[CEP:2] [CEP_INV:0]
  • CLK=[CLK:2] [CLK_INV:0]
  • PREG=[0:2]
  • PREG_CLKINVERSION=[0:2]
  • RSTA=[RSTA:2] [RSTA_INV:0]
  • RSTB=[RSTB:2] [RSTB_INV:0]
  • RSTP=[RSTP_INV:0] [RSTP:2]
 RAMB16BWE
  • CLKA=[CLKA_INV:0] [CLKA:16]
  • CLKB=[CLKB_INV:0] [CLKB:16]
  • ENA=[ENA_INV:0] [ENA:16]
  • ENB=[ENB_INV:0] [ENB:16]
  • SSRA=[SSRA_INV:0] [SSRA:16]
  • SSRB=[SSRB_INV:0] [SSRB:16]
  • WEA0=[WEA0:16] [WEA0_INV:0]
  • WEA1=[WEA1:16] [WEA1_INV:0]
  • WEA2=[WEA2:16] [WEA2_INV:0]
  • WEA3=[WEA3_INV:0] [WEA3:16]
  • WEB0=[WEB0:16] [WEB0_INV:0]
  • WEB1=[WEB1:16] [WEB1_INV:0]
  • WEB2=[WEB2_INV:0] [WEB2:16]
  • WEB3=[WEB3:16] [WEB3_INV:0]
 RAMB16BWE_RAMB16BWE
  • CLKA=[CLKA_INV:0] [CLKA:16]
  • CLKB=[CLKB_INV:0] [CLKB:16]
  • DATA_WIDTH_A=[2:16]
  • DATA_WIDTH_B=[2:16]
  • ENA=[ENA_INV:0] [ENA:16]
  • ENB=[ENB_INV:0] [ENB:16]
  • SSRA=[SSRA_INV:0] [SSRA:16]
  • SSRB=[SSRB_INV:0] [SSRB:16]
  • WEA0=[WEA0:16] [WEA0_INV:0]
  • WEA1=[WEA1:16] [WEA1_INV:0]
  • WEA2=[WEA2:16] [WEA2_INV:0]
  • WEA3=[WEA3_INV:0] [WEA3:16]
  • WEB0=[WEB0:16] [WEB0_INV:0]
  • WEB1=[WEB1:16] [WEB1_INV:0]
  • WEB2=[WEB2_INV:0] [WEB2:16]
  • WEB3=[WEB3:16] [WEB3_INV:0]
  • WRITE_MODE_A=[WRITE_FIRST:16]
  • WRITE_MODE_B=[WRITE_FIRST:16]
 SLICEL
  • BX=[BX_INV:2] [BX:606]
  • BY=[BY:365] [BY_INV:8]
  • CE=[CE:1236] [CE_INV:18]
  • CIN=[CIN_INV:0] [CIN:385]
  • CLK=[CLK:1517] [CLK_INV:3]
  • SR=[SR:1089] [SR_INV:58]
 SLICEL_CYMUXF
  • 0=[0:406] [0_INV:0]
  • 1=[1_INV:2] [1:404]
 SLICEL_CYMUXG
  • 0=[0:388] [0_INV:0]
 SLICEL_F5MUX
  • S0=[S0:265] [S0_INV:0]
 SLICEL_F6MUX
  • S0=[S0:6] [S0_INV:0]
 SLICEL_FFX
  • CE=[CE:1123] [CE_INV:8]
  • CK=[CK:1364] [CK_INV:2]
  • D=[D:1366] [D_INV:0]
  • FFX_INIT_ATTR=[INIT0:1340] [INIT1:26]
  • FFX_SR_ATTR=[SRLOW:1346] [SRHIGH:20]
  • LATCH_OR_FF=[FF:1366]
  • REV=[REV_INV:1] [REV:3]
  • SR=[SR:999] [SR_INV:39]
  • SYNC_ATTR=[ASYNC:336] [SYNC:1030]
 SLICEL_FFY
  • CE=[CE:893] [CE_INV:13]
  • CK=[CK:1050] [CK_INV:2]
  • D=[D:1045] [D_INV:7]
  • FFY_INIT_ATTR=[INIT0:1025] [INIT1:27]
  • FFY_SR_ATTR=[SRLOW:1029] [SRHIGH:23]
  • LATCH_OR_FF=[FF:1052]
  • SR=[SR:757] [SR_INV:46]
  • SYNC_ATTR=[ASYNC:261] [SYNC:791]
 SLICEL_XORF
  • 1=[1_INV:2] [1:361]
 SLICEM
  • BY=[BY:136] [BY_INV:0]
  • CLK=[CLK:136] [CLK_INV:0]
  • SR=[SR:136] [SR_INV:0]
 SLICEM_F
  • DI=[DI:136] [DI_INV:0]
  • F_ATTR=[DUAL_PORT:136]
  • LUT_OR_MEM=[RAM:136]
 SLICEM_G
  • DI=[DI:136] [DI_INV:0]
  • G_ATTR=[DUAL_PORT:136]
  • LUT_OR_MEM=[RAM:136]
 SLICEM_WSGEN
  • CK=[CK:136] [CK_INV:0]
  • WE=[WE_INV:0] [WE:136]
 
Pin Data
BUFGMUX
  • I0=2
  • O=2
  • S=2
 BUFGMUX_GCLKMUX
  • I0=2
  • OUT=2
  • S=2
 BUFGMUX_GCLK_BUFFER
  • IN=2
  • OUT=2
 DCM
  • CLK0=1
  • CLKFB=1
  • CLKFX=1
  • CLKIN=1
  • LOCKED=1
  • PSCLK=1
  • PSEN=1
  • PSINCDEC=1
  • RST=1
  • STATUS2=1
 DCM_DCM
  • CLK0=1
  • CLKFB=1
  • CLKFX=1
  • CLKIN=1
  • LOCKED=1
  • PSCLK=1
  • PSEN=1
  • PSINCDEC=1
  • RST=1
  • STATUS2=1
 IBUF
  • I=5
  • PAD=5
 IBUF_DELAY_ADJ_BBOX
  • IBUF_OUT=5
  • SEL_IN=5
 IBUF_INBUF
  • IN=5
  • OUT=5
 IBUF_PAD
  • PAD=5
 IOB
  • I=21
  • ICE=16
  • ICLK1=16
  • IQ1=16
  • O1=50
  • OCE=4
  • OTCLK1=6
  • PAD=50
  • SR=1
  • T1=21
  • TCE=1
 IOB_DELAY_ADJ_BBOX
  • IBUF_OUT=21
  • IFD_OUT=16
  • SEL_IN=21
 IOB_IFF1
  • CE=16
  • CK=16
  • D=16
  • Q=16
 IOB_INBUF
  • IN=21
  • OUT=21
 IOB_OFF1
  • CE=4
  • CK=5
  • D=5
  • Q=5
 IOB_OUTBUF
  • IN=50
  • OUT=50
  • TRI=21
 IOB_PAD
  • PAD=50
 IOB_TFF1
  • CE=1
  • CK=1
  • D=1
  • Q=1
  • SR=1
 MULT18X18SIO
  • A0=2
  • A1=2
  • A10=2
  • A11=2
  • A12=2
  • A13=2
  • A14=2
  • A15=2
  • A16=2
  • A17=2
  • A2=2
  • A3=2
  • A4=2
  • A5=2
  • A6=2
  • A7=2
  • A8=2
  • A9=2
  • B0=2
  • B1=2
  • B10=2
  • B11=2
  • B12=2
  • B13=2
  • B14=2
  • B15=2
  • B16=2
  • B17=2
  • B2=2
  • B3=2
  • B4=2
  • B5=2
  • B6=2
  • B7=2
  • B8=2
  • B9=2
  • CEA=2
  • CEB=2
  • CEP=2
  • CLK=2
  • P0=2
  • P1=2
  • P10=2
  • P11=2
  • P12=2
  • P13=2
  • P14=2
  • P15=2
  • P16=2
  • P17=2
  • P18=2
  • P19=1
  • P2=2
  • P20=1
  • P3=2
  • P4=2
  • P5=2
  • P6=2
  • P7=2
  • P8=2
  • P9=2
  • RSTA=2
  • RSTB=2
  • RSTP=2
 MULT18X18SIO_MULT18X18SIO
  • A0=2
  • A1=2
  • A10=2
  • A11=2
  • A12=2
  • A13=2
  • A14=2
  • A15=2
  • A16=2
  • A17=2
  • A2=2
  • A3=2
  • A4=2
  • A5=2
  • A6=2
  • A7=2
  • A8=2
  • A9=2
  • B0=2
  • B1=2
  • B10=2
  • B11=2
  • B12=2
  • B13=2
  • B14=2
  • B15=2
  • B16=2
  • B17=2
  • B2=2
  • B3=2
  • B4=2
  • B5=2
  • B6=2
  • B7=2
  • B8=2
  • B9=2
  • CEA=2
  • CEB=2
  • CEP=2
  • CLK=2
  • P0=2
  • P1=2
  • P10=2
  • P11=2
  • P12=2
  • P13=2
  • P14=2
  • P15=2
  • P16=2
  • P17=2
  • P18=2
  • P19=1
  • P2=2
  • P20=1
  • P3=2
  • P4=2
  • P5=2
  • P6=2
  • P7=2
  • P8=2
  • P9=2
  • RSTA=2
  • RSTB=2
  • RSTP=2
 RAMB16BWE
  • ADDRA1=16
  • ADDRA10=16
  • ADDRA11=16
  • ADDRA12=16
  • ADDRA13=16
  • ADDRA2=16
  • ADDRA3=16
  • ADDRA4=16
  • ADDRA5=16
  • ADDRA6=16
  • ADDRA7=16
  • ADDRA8=16
  • ADDRA9=16
  • ADDRB1=16
  • ADDRB10=16
  • ADDRB11=16
  • ADDRB12=16
  • ADDRB13=16
  • ADDRB2=16
  • ADDRB3=16
  • ADDRB4=16
  • ADDRB5=16
  • ADDRB6=16
  • ADDRB7=16
  • ADDRB8=16
  • ADDRB9=16
  • CLKA=16
  • CLKB=16
  • DIB0=16
  • DIB1=16
  • DOA0=16
  • DOA1=16
  • DOB0=16
  • DOB1=16
  • ENA=16
  • ENB=16
  • SSRA=16
  • SSRB=16
  • WEA0=16
  • WEA1=16
  • WEA2=16
  • WEA3=16
  • WEB0=16
  • WEB1=16
  • WEB2=16
  • WEB3=16
 RAMB16BWE_RAMB16BWE
  • ADDRA1=16
  • ADDRA10=16
  • ADDRA11=16
  • ADDRA12=16
  • ADDRA13=16
  • ADDRA2=16
  • ADDRA3=16
  • ADDRA4=16
  • ADDRA5=16
  • ADDRA6=16
  • ADDRA7=16
  • ADDRA8=16
  • ADDRA9=16
  • ADDRB1=16
  • ADDRB10=16
  • ADDRB11=16
  • ADDRB12=16
  • ADDRB13=16
  • ADDRB2=16
  • ADDRB3=16
  • ADDRB4=16
  • ADDRB5=16
  • ADDRB6=16
  • ADDRB7=16
  • ADDRB8=16
  • ADDRB9=16
  • CLKA=16
  • CLKB=16
  • DIB0=16
  • DIB1=16
  • DOA0=16
  • DOA1=16
  • DOB0=16
  • DOB1=16
  • ENA=16
  • ENB=16
  • SSRA=16
  • SSRB=16
  • WEA0=16
  • WEA1=16
  • WEA2=16
  • WEA3=16
  • WEB0=16
  • WEB1=16
  • WEB2=16
  • WEB3=16
 SLICEL
  • BX=608
  • BY=373
  • CE=1254
  • CIN=385
  • CLK=1520
  • COUT=388
  • F1=2729
  • F2=2548
  • F3=2155
  • F4=1271
  • F5=12
  • FXINA=6
  • FXINB=6
  • G1=2658
  • G2=2484
  • G3=2052
  • G4=1220
  • SR=1147
  • X=1740
  • XQ=1366
  • Y=1770
  • YQ=1052
 SLICEL_C1VDD
  • 1=37
 SLICEL_C2VDD
  • 1=36
 SLICEL_CYMUXF
  • 0=406
  • 1=406
  • OUT=406
  • S0=406
 SLICEL_CYMUXG
  • 0=388
  • 1=388
  • OUT=388
  • S0=388
 SLICEL_F
  • A1=2721
  • A2=2547
  • A3=2155
  • A4=1271
  • D=2731
 SLICEL_F5MUX
  • F=265
  • G=265
  • OUT=265
  • S0=265
 SLICEL_F6MUX
  • 0=6
  • 1=6
  • OUT=6
  • S0=6
 SLICEL_FAND
  • 0=22
  • 1=22
  • O=22
 SLICEL_FFX
  • CE=1131
  • CK=1366
  • D=1366
  • Q=1366
  • REV=4
  • SR=1038
 SLICEL_FFY
  • CE=906
  • CK=1052
  • D=1052
  • Q=1052
  • SR=803
 SLICEL_G
  • A1=2649
  • A2=2482
  • A3=2052
  • A4=1220
  • D=2658
 SLICEL_GAND
  • 0=21
  • 1=21
  • O=21
 SLICEL_GNDF
  • 0=258
 SLICEL_GNDG
  • 0=245
 SLICEL_XORF
  • 0=363
  • 1=363
  • O=363
 SLICEL_XORG
  • 0=361
  • 1=361
  • O=361
 SLICEM
  • BY=136
  • CLK=136
  • F1=136
  • F2=136
  • F3=136
  • F4=136
  • G1=136
  • G2=136
  • G3=136
  • G4=136
  • SR=136
  • X=136
 SLICEM_F
  • A1=136
  • A2=136
  • A3=136
  • A4=136
  • D=136
  • DI=136
  • WF1=136
  • WF2=136
  • WF3=136
  • WF4=136
  • WS=136
 SLICEM_G
  • A1=136
  • A2=136
  • A3=136
  • A4=136
  • DI=136
  • WG1=136
  • WG2=136
  • WG3=136
  • WG4=136
  • WS=136
 SLICEM_WSGEN
  • CK=136
  • WE=136
  • WSF=136
  • WSG=136
 
Software Quality
Run Statistics
Bitgen 12883 12882 0 0 0 0 0
MAP 7027 6829 0 0 0 0 0
NGDBuild 7344 7328 0 0 0 0 0
PAR 6821 6469 322 0 0 0 0
Start 0 0 0 0 0 0 0
_impact 245 241 0 0 0 0 0
bitgen 1 1 0 0 0 0 0
edif2ngd 74495 74491 0 0 0 0 0
map 14 2 0 0 0 0 0
ngc2edif 140 140 0 0 0 0 0
ngcbuild 117 117 0 0 0 0 0
ngdbuild 17 16 0 0 0 0 0
par 2 2 0 0 0 0 0
trce 6475 6471 0 0 0 0 0
xst 7087 6984 0 0 0 0 0
 
Unisim Statistics
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_AND2=198 NGDBUILD_NUM_AND2B1=127 NGDBUILD_NUM_AND3=2 NGDBUILD_NUM_AND3B1=6
NGDBUILD_NUM_AND3B2=8 NGDBUILD_NUM_AND3B3=1 NGDBUILD_NUM_AND4=1 NGDBUILD_NUM_AND4B1=1
NGDBUILD_NUM_AND4B4=1 NGDBUILD_NUM_BUFG=2 NGDBUILD_NUM_DCM_SP=1 NGDBUILD_NUM_FD=27
NGDBUILD_NUM_FDC=3 NGDBUILD_NUM_FDCE=55 NGDBUILD_NUM_FDCPE=1 NGDBUILD_NUM_FDC_1=4
NGDBUILD_NUM_FDE=516 NGDBUILD_NUM_FDP=9 NGDBUILD_NUM_FDPE=3 NGDBUILD_NUM_FDR=366
NGDBUILD_NUM_FDRE=1473 NGDBUILD_NUM_FDRSE=4 NGDBUILD_NUM_FDS=4 NGDBUILD_NUM_FDSE=38
NGDBUILD_NUM_GND=23 NGDBUILD_NUM_IBUF=26 NGDBUILD_NUM_INV=23 NGDBUILD_NUM_LUT1=189
NGDBUILD_NUM_LUT1_L=158 NGDBUILD_NUM_LUT2=578 NGDBUILD_NUM_LUT2_L=268 NGDBUILD_NUM_LUT3=1067
NGDBUILD_NUM_LUT3_L=729 NGDBUILD_NUM_LUT4=1430 NGDBUILD_NUM_LUT4_L=774 NGDBUILD_NUM_MULT18X18SIO=2
NGDBUILD_NUM_MULT_AND=43 NGDBUILD_NUM_MUXCY=15 NGDBUILD_NUM_MUXCY_L=779 NGDBUILD_NUM_MUXF5=265
NGDBUILD_NUM_MUXF6=6 NGDBUILD_NUM_NAND2=2 NGDBUILD_NUM_NOR2=2 NGDBUILD_NUM_OBUF=29
NGDBUILD_NUM_OBUFT=21 NGDBUILD_NUM_OR2=148 NGDBUILD_NUM_OR2B1=5 NGDBUILD_NUM_OR3=4
NGDBUILD_NUM_OR3B1=1 NGDBUILD_NUM_OR3B2=1 NGDBUILD_NUM_OR4=6 NGDBUILD_NUM_OR4B1=1
NGDBUILD_NUM_PULLUP=6 NGDBUILD_NUM_RAMB16BWE=16 NGDBUILD_NUM_VCC=15 NGDBUILD_NUM_XNOR2=16
NGDBUILD_NUM_XORCY=722